1. Field of the Invention
The present invention relates to floating gate memory cells and, more particularly, to a method for programming a single EPROM or FLASH memory cell to store multiple levels of data, i.e., more than a logic "1" and a logic "0".
2. Description of the Related Art
FIG. 1 shows a conventional n-channel, floating gate memory cell 10. As shown in FIG. 1, memory cell 10 includes an n-type source region 12 and an n-type drain region 14 which are formed a distance apart in a p-type substrate 16. The surface area of substrate 16 between the source and drain regions 12 and 14 defines a channel region 18 which is typically doped with additional p-type dopants (typically boron atoms) to adjust the threshold voltage of the cell.
Formed over the channel region 18 is a stacked gate structure which includes a gate oxide layer 20, a polysilicon floating gate 22 formed over gate oxide layer 20, an oxide-nitride-oxide (ONO) layer 24 formed over floating gate 22, and a polysilicon control gate 26 formed over ONO layer 24.
With 0.8 micron technology, where the channel length is approximately 0.8 microns, memory cell 10 is conventionally programmed to store one of two logic levels, i.e., a logic "1" or a logic "0", by grounding the source region 12 and substrate 16, applying a bias voltage VD in the range of 6-8 volts to the drain region 14, and applying a programming voltage VG of approximately 12 volts to control gate 26.
FIG. 2 shows the result of these bias conditions on memory cell 10. As shown in FIG. 2, when the programming voltage is applied to control gate 26, a positive potential is induced on floating gate 22. The positive potential on floating gate 22, in turn, attracts electrons from the doped p-type atoms in the channel region 18 to the surface of substrate 16 to form a channel 30, and also repels holes from the doped p-type impurity atoms to form a depletion region 32.
When the bias voltage VD is applied to the drain region 14, an electric field is established between the source and drain regions 12 and 14 in channel region 30 and depletion region 32. The electric field accelerates the electrons in channel 30 which, in turn, have ionizing collisions that form "channel hot electrons". The positive potential of floating gate 22 attracts these channel hot electrons which penetrate gate oxide layer 20 and begin accumulating on floating gate 22.
The negative charge on floating gate 22 that results from the accumulated electrons, in turn, directly corresponds to the threshold voltage required to induce a defined current to flow through memory cell 10. Thus, when a large negative charge has accumulated on floating gate 22, the threshold voltage of the cell is large because a larger positive voltage must be applied to control gate 26 to compensate for the negative charge on floating gate 22. Similarly, if the cell has not been programmed, the threshold voltage is small because a smaller voltage will induce current to flow through the cell.
The above-described process is self-limiting because, as the number of electrons on floating gate 22 increases, the potential of floating gate 22 decreases until the potential on floating gate 22 is insufficient to create channel 30.
When memory cell 10 is read, a reference threshold voltage is applied to control gate 26 to again induce a potential on floating gate 22. If memory cell 10 has not been programmed, the positive potential on floating gate 22 will cause channel 30 to again be formed. As a result, current flows from the drain region 14 to the source region 12 through channel 30.
If memory cell 10 has been programmed, the potential on floating gate 22 is reduced by the accumulated electrons so that a much smaller current flows through channel 30. By then comparing the current to a reference current, the magnitude of the current can be interpreted to be either a logic "1" or a logic "0". In other words, if the threshold voltage of the cell is larger than the reference threshold voltage, then one logic level is present, whereas if the threshold voltage of the cell is smaller than the reference threshold voltage, then the other logic level is present.
Historically, the density of memory arrays has been increased by reducing the feature sizes of the cells. As the feature sizes become ever smaller, however, this approach becomes more costly and more difficult to implement.
Another approach to increasing the density of a memory array is to program each cell to store more than two logic levels. As stated above, memory cells are conventionally programmed to store one of two logic levels, i.e., a logic "1" or a logic "0". However, if each memory cell could be programmed to store a logic "00", "01", "10", or "11", then the density of an array could be doubled without changing the physical size of the array.
In theory, multi-level programming could be accomplished by varying the length of time that the programming voltage is applied to the control gate. Thus, for example, if the programming voltage was applied for a first time period, the floating gate would reach a corresponding first negative charge level. Similarly, if the programming voltage was applied for either a second, third, or fourth time period, the floating gate would reach either a corresponding second, third, or fourth negative charge level.
The problem with this type of multi-level programming, however, is that it is difficult to precisely control the number of electrons that accumulate on the floating gate because the reduced floating gate potential that results from the electrons accumulating on the floating gate causes fewer electrons to be attracted to the floating gate, thereby causing the number of electrons accumulated on the floating gate to vary over time. The greater the variation, the more difficult it is to compare current levels during a read operation and determine which logic level is present. As a result, there is a need for a method to accurately program a cell to store multiple logic levels.